NXP Semiconductors /MIMXRT1011 /IOMUXC_GPR /GPR5

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Interpret as GPR5

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (WDOG1_MASK_0)WDOG1_MASK 0 (WDOG2_MASK_0)WDOG2_MASK 0 (VREF_1M_CLK_GPT1_0)VREF_1M_CLK_GPT1 0 (VREF_1M_CLK_GPT2_0)VREF_1M_CLK_GPT2

VREF_1M_CLK_GPT2=VREF_1M_CLK_GPT2_0, VREF_1M_CLK_GPT1=VREF_1M_CLK_GPT1_0, WDOG1_MASK=WDOG1_MASK_0, WDOG2_MASK=WDOG2_MASK_0

Description

GPR5 General Purpose Register

Fields

WDOG1_MASK

WDOG1 Timeout Mask

0 (WDOG1_MASK_0): WDOG1 Timeout behaves normally

1 (WDOG1_MASK_1): WDOG1 Timeout is masked

WDOG2_MASK

WDOG2 Timeout Mask

0 (WDOG2_MASK_0): WDOG2 Timeout behaves normally

1 (WDOG2_MASK_1): WDOG2 Timeout is masked

VREF_1M_CLK_GPT1

GPT1 1 MHz clock source select

0 (VREF_1M_CLK_GPT1_0): GPT1 ipg_clk_highfreq driven by IPG_PERCLK

1 (VREF_1M_CLK_GPT1_1): GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock

VREF_1M_CLK_GPT2

GPT2 1 MHz clock source select

0 (VREF_1M_CLK_GPT2_0): GPT2 ipg_clk_highfreq driven by IPG_PERCLK

1 (VREF_1M_CLK_GPT2_1): GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock

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